Vendor: NTLab Category: PLL

10MHz to 50MHz fractional-N PLL synthesizer

APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50M…

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UMC 22nm ULP Silicon Proven View all specifications

Overview

APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50MHz XTAL oscillator, which is also able to work as an input signal buffer in the same frequency range. The internal 2.5GHz high frequency VCO provides both excellent phase noise performance and ultra-fine frequency tuning step. The PLL is supplied from 1.8V input voltage down converted by embedded LDOs with low noise and high PSRR. The embedded Bias block provides a low noise and high PSRR voltage and current references to PMU, PLL core and XTAL blocks, as well as it outputs a voltage reference 1.0V for external purposes with up to 10uA load.

Key features

  • UMC 22nm ULP technology
  • 1.8V IO power supply
  • Double 0.8/1.0V Core power supply
  • Embedded low noise bias
  • Reference frequency 10MHz÷50MHz
  • 2.25GHz/2.46GHz VCO
  • Reference frequency accuracy: ±20ppm
  • Supported audio clock sample frequencies: 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz
  • Audio clock frequency generation (MCLK):
    • - 11.2896MHz, 12.288MHz, 22.5792MHz, 24.576MHz, 45.1584MHz, 49.152MHz
  • Output frequency fine tuning range: ±1000ppm
  • Output frequency fine tuning step: 1ppb
  • RMS jitter: 2ps@20Hz–20kHz
  • APLL current consumption:
    • - 3.8mA in active PLL mode
    • - 0.5mA in standby mode (XTAL and PMU are working)
  • Embedded high-performance PMU:
  • Adjustable output voltage
  • 10mA load current
  • 0.8V power supply for external blocks
  • LDO PSRR: -65dB @1kHz
  • LDO noise: 40 nV/?Hz @10kHz
  • APLL area with pads: 0.95mm2 actual silicon value

Block Diagram

022UMC_PLL_01 block diagram

Applications

  • Audio applications
  • DAC and ADC Clocks
  • I2S and I8S clocks

What’s Included?

  • Schematic or NetList
  • Abstract view (.lef and .lib files)
  • Layout (optional)
  • Behavioral model (for functional verification)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
UMC 22nm ULP Silicon Proven

Specifications

Identity

Part Number
022UMC_PLL_01
Vendor
NTLab

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
Contact NTLab

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Frequently asked questions about PLL IP cores

What is 10MHz to 50MHz fractional-N PLL synthesizer?

10MHz to 50MHz fractional-N PLL synthesizer is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for umc Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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