Vendor: NTLab Category: PLL

50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL

055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.

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SMIC 55nm LL Silicon Proven View all specifications

Overview

055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz. It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency. LO output signal is CMOS compatible.

Silicon area: 0.018 mm2.

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Condition

Value

 

Unit

min

typ.

max

Supply voltage

VVCC12

-

1.08

1.2

1.32

V

Temperature range

Tj

-

-40

25

125

ºС

VCO control voltage

Vctrl

-

0.1

-

1.05

V

 

Current consumption

 

IVCC12

Fout = 400MHz

-

190

250

 

uA

Fout = 800MHz

-

335

470

Reference current

Iref_1uA

-

-

1

-

uA

Current consumption in standby mode

 

Istb

 

-

 

-

 

0.04

 

11.5

 

uA

Reference signal logic-level high

 

VRefH

 

 

CMOS

 

0.8*VVCC12

 

-

 

VVCC12

 

 

V

Reference signal logic-level low

 

VRefL

 

0

 

-

 

0.2

Input logic-level high

VIH_VCC12

For digitalinputs

0.8*VVCC12

-

VVCC12

 

V

Input logic-level low

VIL_VCC12

0

-

0.2

Output logic-level high

VOH_VCC12

For digital outputs

0.8*VVCC12

-

VVCC12

 

V

Output logic-level low

VOL_VCC12

0

-

0.2

VCO frequency

FVCO

-

400

-

800

MHz

Output frequency

FLO

-

50

-

800

MHz

LO duty cycle

DCLO

-

40

50

60

%

 

Phase noise

 

PNLO

FLO = 400MHz at 1MHz

-

-96.2

-

 

dBc/Hz

FLO = 800MHz at 1MHz

-

-92.5

-

Reference frequency

Fref

-

4

6

20

MHz

Reference clock duty cycle

 

DCref

 

-

 

40

 

50

 

60

 

%

Comparison frequency

Fcomp

-

4

-

20

MHz

Lock time

Tlock

-

-

9

14

us

Lock detector accuracy

Serr

-

15

20

27

ns

Lock monitoring period

MP

Tcomp = 1/Fcomp

-

32*Tcomp

-

us

Block Diagram

055SMIC_PLL_01 block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL Silicon Proven

Specifications

Identity

Part Number
055SMIC_PLL_01
Vendor
NTLab

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
Contact NTLab

Learn more about PLL IP core

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Frequently asked questions about PLL IP cores

What is 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL?

50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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