VESA DSC 1.1 Encoder IP Core for Automotive Displays (ASIL-B Ready ISO 26262 Certified)
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder.
- VESA DSC
- VESA DSC 1.1
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
VESA DSC 1.1 Encoder IP Core for Automotive Displays (ASIL-B Ready ISO 26262 Certified)
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder.
The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.
400G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
Empowering customers to thrive in the AI Era, INNOSILICON™ introduces its most 112G SerDes (Serializer/Deserializer) and Controll…
The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interf…
USB 3.1 Gen1 / Gen2 Device Controller IP
USB 3.1 Device controller is a configurable core and implements the USB 3.1 Device functionality that can be interfaced with thir…
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps.
The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into …
DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.
SENT Protocol IP Core for Automotive Communication
The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller.
USB 2.0 Human Interface Devices Design Platform
The USB 2.0 HID Design Platform is a , integrated solution, dedicated to a wide range of USB-based Human Interface Devices, like …
USB 2.0 Audio Devices Design Platform
The USB 2.0 Audio Design Platform is a , integrated solution, dedicated to USB-based Audio Devices, like microphones and speakers.
The Universal Media Access Controller (UMAC) ensures efficient data flow, low latency, and optimized power usage.
UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
32G PHY in TSMC (N5A, N3A) for Automotive
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…