Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library C30.
- UMC
- 28nm
- HPC
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library C30.
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 HVT).
Standard Cell (ECO) Library IP, RVT, UMC 65nm SP process
metal-1 start Gate Array ECO Library for UMC 65nm SP/RVT(FSE0A_D).
Standard Cell (ECO) Library IP, RVT, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LPLUS (C38).
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LMINUS (C30 RVT).
Standard Cell (ECO) Library IP, LVT, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track Standard Generic ECO Cell Library (C35).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Generic Core Cell Library wtih LPLUS (C38).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Cell Library with LMINUS (C30).
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process high performance 12-Track Metal1 Start ECO Core Cell Library.
Standard Cell (ECO) Library IP, HVT, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library C35.
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process high performance 12-Track Metal1 Start ECO Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process
UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library.