UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
- UMC
- 55nm
SRAM IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support fast on-chip volatile storage for caches, buffers, and tightly coupled memories, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare SRAM IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing processors, accelerators, embedded SoCs, or high-speed control systems, you can find the right SRAM IP for your application.
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm eFlash Single-Port SRAM memory compiler
UMC 55nm eFlash Single-Port SRAM memory compiler
55 SP Dual Port SRAM compiler with 1P4M metal option
55 SP Dual Port SRAM compiler with 1P4M metal option
UMC 90nm SPLVT ultra-high speed 1-port SRAM
UMC 90nm SPLVT ultra-high speed 1-port SRAM
UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler
UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler
UMC 28nm HPC Process dual port SRAM with power gating
UMC 28nm HPC Process dual port SRAM with power gating
UMC 28nm HPC process PG Dual Port SRAM with LVT
UMC 28nm HPC process PG Dual Port SRAM with LVT
UMC 28nm HPC process PG-Dual Port SRAM with LVT
UMC 28nm HPC process PG-Dual Port SRAM with LVT
UMC 28nm HPC process Dual Port SRAM with Power gating
UMC 28nm HPC process Dual Port SRAM with Power gating
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.
28nm HPM SP-SRAM with Row and 2 Column Repair
28nm HPM SP-SRAM with Row and 2 Column Repair
28nm HPM SP-SRAM with row and 1 column repair
28nm HPM SP-SRAM with row and 1 column repair
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair