Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
- UMC
- 130nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 20M-200MHz, output 50M-100MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Linear Regulator IP, Output: 3.3V/240mA, UMC 0.18um LL process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
Voltage detector for flash protect, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
VDT for MMC, UMC 0.18um LL Logic process.
Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.18um G2 process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.18um GII Logic process.
10-Bit 44MSPS dual channel differential current output Digital-to-Analog converter, UMC 0.18um GII Logic process.
A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process
10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process.
A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process
10-Bit 40MSPS Differential Analog-to-Digital converter, UMC 0.18um Mixed-Mode process.
Voltage Detector IP, 3 Levels, UMC 0.18um G2 process
3-level detector for MMC flash storage, VCCA=3.3V, Ivcca=65uA, UMC 0.18um GII Logic process.
Voltage Detector IP, UMC 0.25um Logic process
0.25um process 2 level voltage detector, UMC 0.25um Logic process.
Band Gap IP, Input: 1.2V - 3.3V, VBG=0.615V, UMC 0.18um G2 process
VBG=0.615V, VCCAH=3.3V, VCCAH_min=1.2V, Ivccah=25uA, UMC 0.18um GII Logic process.
Band Gap IP, Input: 1.0V - 1.2V, VBG=0.8V, UMC 0.13um LL/FSG process
VBG=0.8V, VCCA=1.2V, VCCA_min=1.0V, Ivcca=45uA, UMC 0.13um LL Logic/FSG process.
Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.15um SP process
VBG=0.615V, VCCA=1.5V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.15um SP Logic process.