PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
- UMC
- 110nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process.
PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 40nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 28nm HPM process
Input 25-66MHz, output 400-800MHz, frequency synthesizable PLL, UMC 28nm HPM Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/FSG Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 40nm LP process
Input 20M-200MHz, output 500M-1GHz, frequency synthesizable PLL, UMC 40nm LP/RVT Low-K Logic process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequenc…
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequenc…
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequenc…
PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 96MHz - 180MHz, UMC 0.11um HS/AE process
Input 12MHz, output 96M~180MHz, 1.08~1.32V frequency synthesizable PLL, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.