Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
- UMC
- 28nm
- HPC
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x000D_ _x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x000D_
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz.
Linear Regulator IP, UMC 0.18um G2 process
Input 2.7V~3.6V, Output=1.8V,Loading 50mA Regulator, UMC 0.18um GII 1.8V/3.3V Process
Linear Regulator IP, UMC 0.11um HS/AE process
3.3V to 1.2V Capacitor-Free Linear Regulator with 100mA driving capability, UMC 0.11um HS/AE (AL Enhancement) Logic Process
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process
Input 1.0V-3.6V, VBG=0.75V, Band Gap, UMC 55nm ULP Low-K Logic process
Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process
Vrr=2.81V Vfr=2.81V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset,special request, UMC 55nm SP/RVT LowK Logic Process
Power on Reset IP, UMC 0.25um MS process
Vrr=1.6V Vfr=1.4V, core type, Power On Reset with tunable reset time by external capacitor, UMC 0.25um Logic/MMC process.
Power on Reset IP, UMC 0.25um process
Power on Reset with Vrr and Vfr., Power On Reset, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.25um process
Power on Reset with Vrr and Vfr., Power On Reset, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.25um process
Power on reset using 0.25um process, A-type IO, Urr=1.8V, Ufr=1.6V, UMC 0.25um Logic process.
Power on Reset IP, UMC 0.11um eFlash process
Power on reset(POR) block, UMC 0.11um e-flash process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V Vfr=2.0V, B type IO, input VCCK=1.2V VCC3IO=3.3V, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.