Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
Wide Range Programmable Integer PLL on UMC L130EHS
The wide range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplic…
High Precision RC Oscillator - UMC 0.18um
Fully integrated 4MHz to 256MHz High Precision RC Oscillator
8MHz RC oscillator on UMC 55nm
he present IP is a low dissipation and high precision relaxation oscillator.
Low-Speed 40KHz RC oscillator on UMC 55nm
The present IP is a low power and low speed internal RC oscillator circuit (LSI RC OSC), used to drive the independent watchdog (…
Integer-N PLL, 32M ~ 256MHz on UMC 55nm
This present IP is a Phase Locked Loop (PLL) circuit.
UMC 0.11um SP/AE (AL Advanced Enhancement) Logic Process High-Freq. OSC BOAC I/O.
UMC 0.11um SP/AE (AL Enhancement) Logic Process High-Freq.
UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process High-Freq0. OSC BOAC I/O.
UMC 0.11um LL/AE (AL Enhancement) Logic Process High-Freq0.
UMC 55nm e-flash Logic Process OSC High IO Library
UMC 55nm e-flash Logic Process OSC High IO Library
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz …
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode.
IP name: FXS2D101HH0L Area: 300um*300um
IP name: FXS2D101HH0L Area: 300um*300um