WebM - Open Web Media Project
•
HQ:
Finland
WebM’s G2 VP9 Decoder IP is the latest addition to WebM family of hardware IP products for multimedia system-on-chip designs.
- TSMC
- 28nm
- Silicon Proven
Compare 15 Video Processing IP Cores for TSMC from 3 vendors
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Cadence Design Systems, Inc.• HQ: USA
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
- TSMC
- 7nm
- N7+
- Silicon Proven
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112G-ELR PAM4 SerDes PHY - TSMC 5nm
Cadence Design Systems, Inc.• HQ: USA112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels…
- TSMC
- 5nm
- N5
- Silicon Proven
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224G-LR SerDes PHY enables 1.6T and 800G networks
Cadence Design Systems, Inc.• HQ: USAThe ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rapid growth of high-speed I/O capa…
- TSMC
- 3nm
- N3A
- Available on request
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Cadence Design Systems, Inc.• HQ: USA
The 56G Long-Reach (LR) SerDes PHY provides exceptional performance with best-in-class power and area, making it ideal for machin…
- TSMC
- 7nm
- N7+
- Silicon Proven
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112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
Cadence Design Systems, Inc.• HQ: USAIn data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, …
- TSMC
- 7nm
- N7+
- Silicon Proven
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Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 28nm
- HPC
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Programmable Low Power SERDES Receiver on TSMC CLN65LP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 65nm
- LP
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Programmable Low Power SERDES on TSMC CLN40G
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 40nm
- G
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Programmable Low Power SERDES on TSMC CLN28HPL
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 28nm
- HPL
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Chip-to-Chip IO Buffer on TSMC CLN6FF
Analog Bits Inc.• HQ: USAThe Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
- TSMC
- 6nm
- N6FF
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Chip-to-Chip IO Buffer on TSMC CLN5A
Analog Bits Inc.• HQ: USAThe Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
- TSMC
- 5nm
- N5A
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Chip-to-Chip IO Buffer on TSMC CLN5
Analog Bits Inc.• HQ: USAThe Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
- TSMC
- 5nm
- N5
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Chip-to-Chip IO Buffer on TSMC CLN4P
Analog Bits Inc.• HQ: USAThe Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
- TSMC
- 4nm
- N4P
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Analog Bits Inc.• HQ: USA
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
- TSMC
- 7nm
- N7FF