Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet …
- TSMC
- 28nm
Analog I/O Pad Library IP cores provide the pad-level interface between silicon and the package or board environment in modern SoC and ASIC designs.
These IP cores support pad cells optimized for analog signal integrity, ESD resilience, and mixed-signal board connectivity, helping designers create robust I/O implementations across digital, analog, and high-speed domains
This catalog allows you to compare Analog I/O Pad Library IP cores from leading vendors based on signal integrity, robustness, integration fit, and process node compatibility.
Whether you are designing analog front ends, sensor systems, RF subsystems, or mixed-signal SoCs, you can find the right Analog I/O Pad Library IP for your application.
Certus Semiconductor has a long history of working across a broad range of technology nodes from 180nm down to the latest FinFet …
HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
A TSMC 28nm HPM/HPC/HPC+ Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, 5V I2C ODIO, 1.8V & 3.3V Analog Cells, ESD and mo…
1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF s…
1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD…
Multi-Voltage GPIO 5V ODIO and Analog/RF I/Os in TSMC 65nm
1V/3.3V GPIO with I2C ODIO and 3.3V & 5V Analog Cells in TSMC 65nm Key attributes of this IO library include dual independent IO …
1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells an…
Wirebond Digital and Analog Library in TSMC 65nm
A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.
1.8V GPIO, 1.8V & 3.3V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with associated ESD cells.
SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
The DDR2 / DDR3 library includes the combo driver / receiver cells and a full complement of power and support cells for both sing…
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Taiwan Semiconductor Manufactur…
Specialed 20V Analog I/O in TSMC 55nm
A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS This silicon-proven TSMC 55nm LP 20V ESD cell is a high-vo…
Contain supply cells, power management, ring building, analog cells for TSMC N4P 1.8V IO Platform MS Add-on
Contain supply cells, power management, ring building, analog cells for TSMC N4P 1.8V IO Platform
Contain supply cells, power management, ring building, analog cells for TSMC N4P 1.8V IO Platform
Contain supply cells, power management, ring building, analog cells for TSMC N5A 1.8V IO Platform, New Frame MS add-on
Contain supply cells, power management, ring building, analog cells for TSMC N5A 1.8V IO Platform, New Frame
Contain supply cells, power management, ring building, analog cells for TSMC N5 1.8V IO, New Frame Additional MS
Contain supply cells, power management, ring building, analog cells for TSMC N5 1.8V IO Platform, New Frame
Contain supply cells, power management, ring building, analog cells for TSMC N5 1.8V IO Platform MS
Contain supply cells, power management, ring building, analog cells for TSMC N5 1.8V IO Platform MS