Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
SMIC 55nm Very-High-Speed LVT for PEK(Performance Enhancement Kit)Standard Library.
SMIC 55nm Very-High-Speed LVT for PEK(Performance Enhancement Kit)Standard Library.
SMIC 55nm Very High-Speed RVT Standard Library for Low Leakage Process.
SMIC 55nm Very High-Speed LVT Standard Library for Low Leakage Process.
SMIC 55nm Very High-Speed HVT Standard Library for Low Leakage Process.
SMIC 55nm LL(RVt) ECO cells compatible with VHS standard cell library.
SMIC 55nm LL(RVt) ECO cells compatible with HS standard cell library.
SMIC 55nm LL(LVt) ECO cells compatible with VHS standard cell library.
SMIC 55nm LL(LVt) ECO cells compatible with HS standard cell library.
SMIC 55nm LL(HVt) ECO cells compatible with VHS standard cell library.
SMIC 55nm High-Speed RVT Standard Library for Power Management Kit.
SMIC 55nm High-Speed RVT Standard Library for Power Management Kit.
SMIC 55nm High-Speed RVT Standard Library for Low Leakage Process.
SMIC 55nm High-Speed RVT Standard Library for Low Leakage Process.
SMIC 55nm High-Speed LVT Standard Library for Low Leakage Process.
SMIC 55nm High-Speed LVT Standard Library for Low Leakage Process.
SMIC 55nm High-Speed LVT for PEK(Performance Enhancement Kit)Standard Library.
SMIC 55nm High-Speed HVT Standard Library for Low Leakage Process.
SMIC 55nm High-Speed HVT Standard Library for Low Leakage Process.
SMIC 55nm LL(RVt) high density standard cells library.
SMIC 55nm LL(RVt) high density standard cells library.
SMIC 55nm LL(LVt) high density standard cells library.
SMIC 55nm LL(LVt) high density standard cells library.
SMIC 55nm LL(HVt) high density standard cells library.
SMIC 55nm LL(HVt) high density standard cells library.
IP
SMIC 55nm LL ESD protection cell
IP
SMIC 55nm LL Standard digital, analog and oscillator IO
IP