Chiplet / Die-To-Die IP Cores for Samsung

Chiplet-based architectures are reshaping advanced SoC design by enabling the integration of multiple dies within a single package. At the core of this transformation are die-to-die (D2D) interconnect IP cores, which provide high-bandwidth, low-latency communication between chiplets.

This page provides a comprehensive overview of chiplet interconnect IP, including leading standards such as UCIe, BoW (Bunch of Wires), and UALink, along with guidance on how to select the right solution for your design. Whether you are developing AI accelerators, HPC processors, or advanced automotive SoCs, choosing the right D2D interface is critical for performance, power efficiency, and scalability.

 
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What are chiplet and die-to-die IP cores?

Die-to-die interconnect IP enables direct communication between chiplets within the same package. Unlike traditional off-chip interfaces, D2D links are optimized for:

  • ultra-high bandwidth density
  • low power per bit
  • minimal latency
  • short-reach communication (typically <10 mm)

These IP cores typically include:

  • PHY layer (electrical signaling)
  • protocol layer (link management, flow control)
  • optional die-to-die adapters (e.g., UCIe stack)

They are used in advanced packaging technologies such as:

  • 2.5D (interposer-based)
  • 3D IC (stacked dies)
  • fan-out packaging

Main chiplet interconnect standards

UCIe (Universal Chiplet Interconnect Express)

UCIe is an emerging industry standard that enables interoperable die-to-die communication across chiplets from different vendors. It supports high bandwidth, low latency, and scalable system integration.

Bunch of Wires (BoW)

BoW is a simpler die-to-die interface standard designed for short-reach communication with low complexity and power consumption.

Proprietary die-to-die interfaces

Many vendors offer custom chiplet interconnect IP optimized for specific performance, power, or packaging requirements.

Key features of chiplet interconnect IP

  • High bandwidth communication between dies
  • Low latency for performance-critical applications
  • Scalability across multiple chiplets
  • Support for advanced packaging (2.5D, 3D integration)
  • Energy-efficient data transfer

How to choose a chiplet or die-to-die IP core

Selecting the right IP depends on system architecture and packaging constraints:

  • Supported standard (UCIe, BoW, or proprietary)
  • Bandwidth and latency requirements
  • Packaging technology (2.5D, 3D, interposer)
  • Power consumption and thermal considerations
  • Integration complexity and ecosystem support

Applications of chiplet and die-to-die IP

  • AI and machine learning accelerators
  • Data center processors
  • High-performance computing (HPC)
  • Networking and telecom systems
  • Advanced heterogeneous SoCs

Compare chiplet and die-to-die IP cores from leading vendors

This catalog provides access to a wide range of chiplet and die-to-die IP cores from leading semiconductor IP providers.

Use filters to compare solutions based on performance, power efficiency, standard support, and integration requirements to find the best interconnect for your chiplet architecture.

Frequently asked questions about Chiplet / Die-to-Die IP cores

What is Chiplet / Die-to-Die IP?

Chiplet interconnect IP enables communication between multiple dies within a single package, replacing traditional monolithic SoC interconnects.

What is the difference between UCIe and BoW?

UCIe is a standardized, scalable interconnect with protocol support, while BoW is a simpler, low-power parallel interface optimized for short distances.

Why are chiplets important?

Chiplets improve yield, reduce cost, and enable modular system design, especially at advanced process nodes.

How do I choose Chiplet / Die-to-Die IP?

Chiplets improve scalability, reduce manufacturing cost, and allow designers to mix different technologies within a single package.

Why use dedicated Chiplet / Die-to-Die IP instead of building it from scratch?

They are used in AI accelerators, data center processors, HPC systems, networking chips, and advanced SoC designs.

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