Low Power All Digital Fractional-N PLL in Samsung 14LPP
Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area.
- Samsung
- 8nm
- 8LPP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and high-speed interfaces such as SerDes.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Low Power All Digital Fractional-N PLL in Samsung 14LPP
Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area.
Temperature Sensor on Samsung 4nm, LN04LPP
The temperature sensor indicates the junction temperature as a 9-bit binary digital code.
Temperature Sensor on Samsung 14nm, LN14LPP
The temperature sensor indicates the junction temperature as a 12-bit binary digital code.
PVT Sensor on Samsung 4nm, LN04LPP
The PVT sensor indicates the junction temperature as a 12-bit binary digital code.
Oscillator on Samsung 28nm LNM28FDS
OSC2802X is a 1V oscillator with output frequency of 240kHz.
Integer PLL on Samsung 8nm LN08LPP
PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Integer PLL on Samsung 28nm LN28FDS
PLL2851X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 8nm LN08LPP
PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 4nm LN04LPP
PLLF0434X is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 28nm LN28FDS
PLL2860X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Adaptive Body Bias Generator on Samsung 28nm LN28FDS
The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.
12-bit ADC on Samsung 8nm LN08LPP
The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports c…
12-bit ADC on Samsung 4nm LN04LPE
ADC0401X is a 1.2-V/0.75-V dual supply voltage 16-channel 12-bit Analog-to-Digital Converter (ADC) that supports conversion rate …
HDMI 2.1 Audio PLL in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
The DeepSub™ pPLL08F is an all digital RF frequency synthesizer PLL featuring industry jitter (sub 300fs), phase noise and compac…
All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP
The DeepSub™ pPLL08F is an all digital RF frequency synthesizer PLL featuring industry jitter (sub 300fs), phase noise and compac…
All Digital Fractional-N PLL for Performance Computing in Samsung 14LPP
The DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical…
All Digital Fractional-N PLL for Performance Computing in Samsung 8LPP
The DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical…
General Purpose All Digital Fractional-N PLL in Samsung 8LPP
The DeepSub™ pPLL02F is a general purpose all digital PLL featuring low-jitter and compact area suitable for many clocking applic…
The High Speed 16GHz PLL generates a low jitter frequency outputs.