GF L12LP 12nm Spread Spectrum PLL - 350MHz-1750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
GF L12LP 12nm Spread Spectrum PLL - 700MHz-3500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
GF L12LP 12nm Multi Phase DLL - 200MHz-1000MHz
The Multi Phase DLL is designed for high-speed interface applications.
GF L12LP 12nm Multi Phase DLL - 400MHz-2000MHz
The Multi Phase DLL is designed for high-speed interface applications.
GF L12LP 12nm Multi Phase DLL - 800MHz-4000MHz
The Multi Phase DLL is designed for high-speed interface applications.
GF L12LP 12nm IoT PLL - 30MHz-1000MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power.
GF L12LP 12nm General Purpose PLL - 400MHz-2000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
GF L12LP 12nm Deskew PLL - 200MHz-1000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LP 12nm Deskew PLL - 400MHz-2000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LP 12nm Deskew PLL - 800MHz-4000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
GF L12LP 12nm DDR DLL - 188MHz-940MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm DDR DLL - 250MHz-1250MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm DDR DLL - 395MHz-1975MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LP 12nm Clock Generator PLL - 200MHz-1000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LP 12nm Clock Generator PLL - 400MHz-2000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
GF L12LP 12nm Clock Generator PLL - 800MHz-4000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
4Kx9 Bits OTP (One-Time Programmable) IP, GF 12LP+ 0.8V/1.8V Process
The ATO0004KX9GF012LPP8ZA is organized as 4K-bits by 9 one-time programmable (OTP).
Embedded OTP (One-Time Programmable) IP, 512x8 bits for 1.5V/5V BCD
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 512x6 bits for 1.8V/6V IC_BCDlite
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 32x32 bits for 1.8V/6V/16V BCDlite
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…