UMC 28HPC 1PRF compiler with HVT peripheral
UMC 28HPC 1PRF compiler with HVT peripheral
- UMC
- 28nm
- HPC
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 28HPC 1PRF compiler with HVT peripheral
UMC 28HPC 1PRF compiler with HVT peripheral
UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler
UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process One Port Register File with LVT
UMC 28nm HPC process One Port Register File with LVT
UMC 28nm HPC process Two Port Register File with LVT and Bank4
UMC 28nm HPC process Two Port Register File with LVT and Bank4
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process 2PRF with Bank2
UMC 28nm HPC process 2PRF with Bank2
UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature
40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.