UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.
- SRAM
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
VeriSilicon HHG 0.11um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for HHGrace Semiconductor Manufacturi…
VeriSilicon HHG 0.11um Low-Power(LP) Process Synchronous Memory Compiler optimized for HHGrace Semiconductor Manufacturing Corpor…
Single Port SRAM Compiler IP, UMC 0.35um SP process
UMC 0.35um Logic process synchronous high speed Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler.
ROM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous diffusion programmed ROM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
ROM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous VIA2 programmed ROM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler.