ROM Compiler IP, UMC 0.18um LL process
UMC 0.18um low leakage(LL) Logic process synchronous Via1 ROM memory compiler.
- UMC
- 180nm
- LL
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
ROM Compiler IP, UMC 0.18um LL process
UMC 0.18um low leakage(LL) Logic process synchronous Via1 ROM memory compiler.
ROM Compiler IP, UMC 0.13um CIS process
UMC 0.13um CMOS Image SensorCu process ROM compiler.
ROM Compiler IP, UMC 0.11um CIS process
UMC 0.11um CMOS Image Sensor process 1P3M VIA1 ROM memory compiler.
ROM Compiler IP, UMC 0.11um EEPROM process
UMC 0.11um EE2PROM/LL process PCode ROM compiler.
ROM Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process Via1 ROM compiler.
ROM Compiler IP, UMC 0.11um LL process
UMC 0.11um EE2PROM AE LL process Pcode ROM.
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler.
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process Two Port Register File.
One Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm low leakage Low-K RVT process synchronous One Port Register File memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler.
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process
UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler.
One Port Register File Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash with peripheral HVT One Port Register File.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Logic process Single Port Register File memory compiler with LVT peripheral.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/HVT Logic process with 6TSRAM (0.242 mm2) 1-port Register File memory compiler.
One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 130nm CMOS Image SensorCu process One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE Logic process Synchronous One Port Register File memory compiler with 1.41um2-Bit cell.
One Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process One Port Register File.