UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler.
- UMC
- 110nm
- HS
SRAM IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support fast on-chip volatile storage for caches, buffers, and tightly coupled memories, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare SRAM IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing processors, accelerators, embedded SoCs, or high-speed control systems, you can find the right SRAM IP for your application.
UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler.
UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
UMC 0.11um BCD process;Single-Port SRAM compiler
UMC 0.11um BCD process;Single-Port SRAM compiler
110nm BCD process Synchronous High-Density Single-Port SRAM Compiler
110nm BCD process Synchronous High-Density Single-Port SRAM Compiler
UMC 28HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell