This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing stan…
This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. Its “Dual-core” architecture doubles the compression speed as compared to our standard baseline JPEG Encoder. The use of JPEG compression allows using very small FPGAs without external memory, leading to very economical systems, and our dual-core architecture allows high resolution and frame rates compression on low cost FPGAs.
Easy to use
Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Platform Designer system (or equivalent). Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Altera Cyclone families, or the Lattice FPGA families (eg ECP3, ECP5, Certus-NX, CertusPro-NX, Crosslink-NX, Mach-XO5 etc) or the Microchip families (Igloo 2 or Polarfire for example).
Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.
Note: some files may require an NDA depending on provider policy.
High-Speed JPEG Video Encoder is a Video Processing IP core from ALSE Advanced Logic Synthesis for Electronics listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
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