Vendor: PrimeSoC Technologies Category: CXL

CXL 3.0 Retimer

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…

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Overview

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical Layer protocol aware Retimer is to execute the Phase 2/3 of the equalization procedure in each direction. Compliant with pipe specification.

Key features

  • Compliant with CXL 3.0/2.0 spec.
  • Compliant with PCIE Gen6/5/4 Specs.
  • Forward mode supported.
  • X1,X2,X4,X8,X16 lanes supported.
  • Lane bifurcation supported.( X16, X8X8, X4X4X4X4, X1)
  • PIPE 40bit Serdes interfaces.
  • APB interface for register configurations.
  • Lane deskew supported.
  • Support for L1 states.
  • SKP OS add/removal.
  • SRIS mode supported.
  • Deemphasis negotiation support at 5GT/s.
  • EI inferences in all modes.
  • Automatic adjustment of data rates in conjunction with upstream and downstream devices.
  • Automatic adjustment of link width in conjunction with upstream and downstream devices.
  • Scrambling, descrambling Support.
  • Customization Support
  • Sync header bypass mode for CXL supported to reduce latency.
  • Drift buffer support* to reduce latency

What’s Included?

  • Verilog soft IP
  • Sample testbench

Specifications

Identity

Part Number
PrimeSOC Retimer
Vendor
PrimeSoC Technologies

Provider

PrimeSoC Technologies
HQ: India
Primesoc Technologies is a Proprietorship Fabless semiconductor company located in Chennai, India , focused on creating First pass silicons and meeting timing in FPGA's. Predominantly focussed on developing High speed internet cores running at 1Ghz frequency and multi lanes. We have expert engineers with 20+ years of experience in developing digital controller cores and providing success silicons.We also validate all our IPs developed using Xilinx and other FPGA platforms and ensure lint clean and synthesis timing met digital controller cores. Being PHY agnostic, we work with any PHY partners to make our digital controller cores matured.
Contact PrimeSoC Technologies

Learn more about CXL IP core

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Frequently asked questions about CXL IP cores

What is CXL 3.0 Retimer?

CXL 3.0 Retimer is a CXL IP core from PrimeSoC Technologies listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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