Vendor: Truechip Solutions Category: CXL

CXL 4 Verification IP

Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…

Contact Provider Request Datasheet

Overview

Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or SoC. Truechip's CXL VIP is fully compliant with latest CXL specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.

Key features

  • Compliant with the CXL 4, 3.2, 2.0 & 1.1 Specifications.
  • Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
  • Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
  • Support for 256B flit in 128GT/s with PCIe Gen 6 as well as 64/32/16/8 GT/s speeds with backward compatibility.
  • Support for different CXL/PCIe Resets.
  • Support for CPI v1.0 (CXL-CACHE/MEM Protocol Interface), CXS B (Credited eXtensible Stream), LPIF v1.1 (Logical PHY Interface) and PIPE v7.0.
  • Support for block level verification.
  • Support for SerDes PIPE Architecture as well as Original PIPE Architecture.
  • Configurable PIPE width support:
    • Original PIPE Arch. - 8, 16, 32, 64
    • SerDes PIPE Arch. - 10, 20, 40, 80, 160.
  • Support for CXL.IO throttling.
  • Support for 128 GT/s speeds with bundled ports.
  • Support for NOP insertion hint performance optimization.
  • Support for Low Pin Count Interface as well as Legacy PIPE Interface.
  • Support for CXL Retry Mechanism.
  • Support for 68B and 256B flit structure.
  • Support for CXL 4 Configuration and Memory-Mapped Registers (For CXL Device and Ports).
  • Support for CXL ALMP transmission and reception to control virtual link state machine and power state transition requests.
  • Support for CXL ACK forcing & Link Layer Credit exchange mechanism.
  • Support for Arbitration among the CXL.IO, CXL.CACHE and CXL.MEM packets with Interleaving of traffic between different CXL protocols.
  • Support for randomization and user controllability in flit packing.
  • Support for power management including the low power L1 with sub-state and L2.
  • Support for CXL in band control message with CXL 4 (Viral & Poison)
  • Support for the Credit exchange field within 256B flit.
  • Support for all 3 coherency models HDM-D, HDM-H and HDM-DB to access HDM memory.
  • Support for PBR TLP for CXL.IO
  • Support for Back Invalidate transactions.
  • Support for RAS error logging & Signalling.
  • Support for Extended Metadata.
  • Support for Bogus, Viral, Global Persistent Flush and Data Object Exchange.
  • Support for IDE.
  • Support for QOS telemetry for memory.
  • Provides two types of routing mechanism. (HBR and PBR).
  • Provides a comprehensive user API (callbacks).
  • Provides two types of 256B flits mechanism (Standard 256B flit & Lopt 256B flit).
  • Provide Compliance test support

Block Diagram

CXL 4 block diagram

Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog.
  • Unique development methodology to ensure the highest levels of quality.
  • 24X5 customer support.
  • Unique and customizable licensing models.
  • Exhaustive set of assertions, cover points with connectivity example for all the components.
  • Consistency of interface, installation, operation, and documentation across all our VIPs.
  • Provide complete solution and easy integration in IP and SoC environment.
  • On-the-fly protocol checking using protocol check functions, static and dynamic assertion.
  • Provides a comprehensive user API (callbacks).
  • Graphical analyzer for easy debugging, regression analysis, performance, statistics and charts.

What’s Included?

  • CXL Host/Device CXL Switch
  • CXL Fabric Manager
  • CXL BFM/Agents for:
    • Host and Device sequences
    • Transaction layer(CXL.IO and CXL.cache, CXL.mem)
    • Link layer(CXL.IO and CXL.cache, CXL.mem)
    • Arbiter/Mux layer
    • PHY layer
  • CXL Monitor and Scoreboard
  • Test Environment & Test Suite:
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Cover Point Tests
    • Compliance Tests
  • Documents:
    • Integration Guide
    • User Manual
    • Quick start Guide, Release Notes
    • FAQs

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
CXL 4
Vendor
Truechip Solutions

Provider

Truechip Solutions
HQ: USA
Truechip is a leading provider of Design and Verification solutions – which help you to accelerate your design, lowering the cost and the risks associated in the development of your ASIC, FPGA and SoC. Truechip is a privately held company, with a global footprint and with a strong and experienced leadership team. Truechip was established in 2008 with a Mission to:
  • To create world class Verification IP Solutions
  • To provide expert consultancy to ASIC & SoC Design companies
  • To design SOCs from Architecture to Working Silicon
Our Vision is to:
  • To be the leading provider of Semiconductor IP Solutions
  • To be a one-stop-shop for Design and Verification
Our Guiding Principles are:
  • Customer Success
  • Commitment to Quality
    • Quality of Products
    • Quality of Engineers
  • Best in class Customer Support
  • Ethics and Integrity
We at Truechip leverage the extensive domain knowledge and expertise from current associations to provide complete set of design and verification solutions to our customers.
Contact Truechip Solutions

Learn more about CXL IP core

Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

Frequently asked questions about CXL IP cores

What is CXL 4 Verification IP?

CXL 4 Verification IP is a CXL IP core from Truechip Solutions listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP