Overview
The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®). Built on top of Cadence's mature industry-leading VIP for PCIe, the CXL VIP provides a complete bus functional model for all three CXL protocols, CXL.io/CXL.mem/CXL.cache, and allows users to verify both CXL host and device designs for all device types (Type 1 – 3) from the very first days of the CXL protocol.
Designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the VIP for CXL runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development, and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. The VIP for CXL can be used as a standalone and as a platform for running TripleCheck tests and supports the latest PIPE specification.
Supported specifications: Compute Express Link Specification 2.0 revision 1.0 and 3.0 revision 1.0.
Provider
Cadence Design Systems, Inc.
HQ:
USA
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Learn more about CXL IP core
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.
Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.
CXL 3.0 allows entire racks of servers to function as a unified, flexible AI fabric. This is especially significant for AI workloads where traditional GPU islands are constrained by memory limits.
The authors present cMPI, the first work to optimize MPI point-to-point communication (both one-sided and two-sided) using CXL memory sharing on a real CXL platform, transforming cross-node communication into memory transactions and data copies within CXL memory, bypassing traditional network protocols.
AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.
