Vendor: PrimeSoC Technologies Category: CXL

CXL 3.0 Dual Mode Controller

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…

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Overview

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards.
CXL cards has same form factor as PCIE , and can be used in same pcie slot.
Primesoc CXL controller cores can work in PCIE mode only(when auto negotiation fails) OR CXL mode having pcie transfers handled as IO flits, along with Cache and Mem transfers. The layers specified in CXL specification Transport, Datalink, Physical layers (digital packet) are implemented in PrimeSOC CXL IP along with PIPE interface logic connecting to PHY, AXI Bridging logic, CPI and CXS to connect to applications.

Key features

  • Compliant to CXL spec V3.X/V2.X.
  • Compliant to PCIE spec 6.0/5.0.
  • CPI Interface support.
  • Compliant to AXI
  • Configurable AXI master, AXI slave. PIPE/FLEX bus.
  • Configurable to work as standalone PCIE DM/CXL DM. Configurable to work as standalone PCIE DM/CXL DM.
  • Configured as PCIE RP/PCIE EP/CXL RP/CXL EP. Native PCIE support.
  • CXL mode / PCIE mode.
  • Static config of PCIE vs CXL.
  • Rate 8/16/32/64 GT/s in CXL mode and 8/16/32/64 in PCIE mode.
  • Configurable X16, X8, X4, X2, X1.
  • Configurable mulltiprotocol of CXL.io/CXL.cache/CXL.mem. Type 1/2/3 CXL devices supported.
  • PCIE Power management using VDM.
  • Configurable credits with granularity of 128 bits. Configurable VCs.
  • ATS support for type1, type2 devices.
  • AER support.
  • Data poisoning.
  • Deferrable writes support.
  • Viral info support.
  • 64B/256B flit support

What’s Included?

  • Verilog soft IP
  • Sample testbenc

Specifications

Identity

Part Number
PrimeSOC CXL
Vendor
PrimeSoC Technologies

Provider

PrimeSoC Technologies
HQ: India
Primesoc Technologies is a Proprietorship Fabless semiconductor company located in Chennai, India , focused on creating First pass silicons and meeting timing in FPGA's. Predominantly focussed on developing High speed internet cores running at 1Ghz frequency and multi lanes. We have expert engineers with 20+ years of experience in developing digital controller cores and providing success silicons.We also validate all our IPs developed using Xilinx and other FPGA platforms and ensure lint clean and synthesis timing met digital controller cores. Being PHY agnostic, we work with any PHY partners to make our digital controller cores matured.
Contact PrimeSoC Technologies

Learn more about CXL IP core

Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

Frequently asked questions about CXL IP cores

What is CXL 3.0 Dual Mode Controller?

CXL 3.0 Dual Mode Controller is a CXL IP core from PrimeSoC Technologies listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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