Vendor: SmartDV Technologies Category: I2C / I3C

SMBUS Assertion IP

SMBUS Assertion IP provides an efficient and smart way to verify the SMBUS designs quickly without a testbench.

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Overview

SMBUS Assertion IP provides an efficient and smart way to verify the SMBUS designs quickly without a testbench. The SmartDV's SMBUS Assertion IP is fully compliant with standard SMBUS Specification.

SMBUS Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SMBUS Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports SMBus specification version 3.0.
    • Supports all the SMBus commands as per the specs.
    • Supports programmable clock frequency of operation.
    • Support ARP command generation and response.
    • Support Timeout detection and generation.
    • Bus-accurate timing.
    • Packet Error Checking support.
    • Wrong ARP Address
    • Unsupported command codes
    • Illegal command lengths
    • Support for multiple instantiations to create complex verification environment.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV SMBUS VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure SMBUS Assertion IP functionality.

Block Diagram

SMBUS AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SMBUS AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about I2C / I3C IP cores

What is SMBUS Assertion IP?

SMBUS Assertion IP is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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