Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.18um GII Logic process.
- UMC
- 180nm
- G
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type, Power On Reset, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 80MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 80MHz.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.75V Vfr=0.65V, input 1.2V, Core type, Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um SP/FSG process
Vrr=0.76V Vfr=0.66V, input 1.2V, Core type, Power On Reset, UMC 0.13um SP Logic(FSG) process.
RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process
DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process
Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 65nm LL Logic/RVT Low-K process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
SMIC 0.18um 3.3v-1.8v Power Regulator
Power Regulator, also called Voltage Regulator, is an on-chip device which provides the suitable power supply for the core from a…
SMIC 0.18µm 1.8v/3.3v Power Switch
The SMIC18_PSW_01 is a PMOS power switch between the main power supply and isolation area.
This IP is a Voltage Detector (VDT) circuit for power management application.
The present IP is a VCC Detector (VDT) circuit which detects the core supply and then sends a corresponding control signal to lev…
GSMC 0.18um 3.3v RC Oscillator
The present IP is a RC oscillator with internal R and C to generate 32¡À20%KHz clock.
GSMC 0.18µm 1.8v/3.3v Power Switch
The GSMC18_PSW_02 is a PMOS power switch between the main power supply and circuit cell.
GSMC 0.18um 3.3v-1.8v Power Regulator
This is a 3.3V to 1.8V power regulator based on GSMC 0.18um 1.8V/3.3V D0 Process.
ADX is an interleaving post-correction digital IP with extreme performance.
10-Bit Current steering DAC 10 bits. - 0.13um
10 bits 80MS/s current steering DAC
The present IP devise a Voltage Detector (VDT) circuit.