Linear Regulator IP, UMC 40nm LP process
3.3V to 1.8V with 150mA driving capability, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
- UMC
- 40nm
- LP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Linear Regulator IP, UMC 40nm LP process
3.3V to 1.8V with 150mA driving capability, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
Linear Regulator IP, UMC 0.13um HS/FSG process
USB 2.0 Two Port PHY, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process 3.3V to 1.2V with 100mA driving capability, Linear Regulator with Capacitor-Free.
Linear Regulator IP, Output: 3.3V/70mA, UMC 0.25um process
3.3V with 70mA driving capability, Istb=75uA Linear Regulator, 0.25um Logic process.
Linear Regulator IP, Output: 3.3V/250mA, UMC 0.25um process
3.3V with 250mA driving capability, Istb=85uA Linear Regulator, UMC 0.25um Logic process.
Linear Regulator IP, Output: 3.3V/150mA, UMC 0.25um process
3.3V with 150mA driving capability, Istb=75uA Linear Regulator, 0.25um Logic process.
Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 2.0V-4.0V, Output: 1.8V / 100mA, UMC 0.18um G2 process
3.3V with 100mA driving capability, Istb=100uA Linear Regulator, 0.18um GII Logic process.
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process
3.3V with 60mA driving capability, Istb=85uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
An ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process.
DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process
Input 360M-720MHz, output 360M-720MHz, DLL, Output 0-180 degree Phase adjustment range.
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process.
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process.