Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.
- UMC
- 110nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output frequency synthesizable PLL, UMC…
Half low pass filter area compare with FXPLL362HJ0G, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400M…
PLL (Frequency Synthesizer) IP, Input: 1MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 1M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 1MHz - 200MHz, Output: 25MHz - 380MHz, UMC 0.18um G2 process
Input 1M-200MHz, output 25M-380MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 120MHz / 540MHz, UMC 40nm LP process
Input 12MHz, output clock1 540MHz and output clock2 120MHz, PLL, UMC 40nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 90nm SP process
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 40nm LP process
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250MHz and 500MHz, UMC 40nm LP/RVT Logic proces…
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process.
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Ji…
Oscillator IP, Output: 5KHz, UMC 55nm SP process
Output frequency 5KHz.
Linear Regulator IP, UMC 90nm SP process
3.3V to 1.0V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.
Linear Regulator IP, UMC 90nm SP process
2.5V to 1.2V/100mA REG, Linear Regulator, UMC 90nm SP/RVT Low-K Logic process.
Linear Regulator IP, UMC 40nm LP process
3.3V to 1.1V/100mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
Linear Regulator IP, UMC 40nm LP process
1.8V and 1.2V input, loading 360mA, 1.1V output with VBG=0.88V Regulator with BYPASS mode, UMC 40nm LP/RVT Low-K Logic process.