Vendor: Alphacore, Inc. Category: PLL

5GHz to 13.5GHz PLL - TSMC 130nm

The PLL13G is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.

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TSMC 130nm BCD+ Silicon Proven View all specifications

Overview

The PLL13G is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.

The PLL13G features a very small area footprint, with exceptional jitter performance in its power/area class and flexible programmability, making this IP ideal for a wide range of general purpose clocking and specialized applications.

The PLL13G is optimized for use in high- performance data converters with wide input bandwidths and/or high sampling rates and advanced interfaces such as PCIe.

The advanced IP block has been designed and verified in TSMC 130nm process.

Key features

  • Input Frequency: ~40MHz
  • Output Frequency: 5.5-13.5 GHz
  • RMS Jitter: <350 fs
  • Supply Voltage: 1.2 V
  • Power: 50.88 mW
  • LC-Tank
  • TSMC 130nm Process
  • Area: 0.75 mm2
  • Radiation-tolerant Version Available: PLL13GRH

Benefits

  • Save time-to-market with our ready-to-go complete product solutions for your commercial or radiation tolerant specifications demands. Our IP uses the latest technology nodes for easy integration, or upon request, can be ported to other nodes.
  • Our IC project teams will become an extension of your system development group, allowing you to focus on your overall end products.

Applications

  • Imaging Systems:
    • CMOS & CCD Image Sensor Readout
    • Infrared FPA Readout
    • Medical Imaging Applications
  • 5G Cellular Base Stations
  • Communications and Networking:
    • Microwave Receivers
    • Radar and Satellite Communications
  • Sensor/Detector Readout Applications
  • Automotive Applications
  • Noisy System-on-Chip environments

What’s Included?

  • Silicon Validation Report
  • Layout View (gds2)
  • Integration Support

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 130nm BCD+ Silicon Proven

Specifications

Identity

Part Number
PLL13G-TS130
Vendor
Alphacore, Inc.

Provider

Alphacore, Inc.
HQ: USA
Alphacore Inc., founded in 2012, is located in the innovative Silicon Desert of Arizona’s technology center. Our engineering and management team combines long histories of delivering innovative RF, analog and mixed signal products and imaging systems for critical systems with business success at companies from multi-nationals to start-ups. Our design team includes seasoned “Radiation Hardened By Design” (RHBD) experts, and we specialize in designing high performance microelectronics, and reliability or authentication tools for niche needs of demanding segments, including scientific research, aerospace, defense, medical imaging, and homeland security.
Contact Alphacore, Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 5GHz to 13.5GHz PLL - TSMC 130nm?

5GHz to 13.5GHz PLL - TSMC 130nm is a PLL IP core from Alphacore, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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