TSMC Cuts Capex by $1 Billion
Cites faster conversion to 16nm
Alan Patterson, EETimes
4/16/2015 05:43 PM EDT
TAIPEI — Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest chip foundry, cut its planned capital expenditure for this year by $1 billion, citing improvements in capital efficiency and a faster-than-expected migration to its leading-edge 16nm process technology.
The company, which in January weighed in with the chip industry’s largest planned layout for expansion this year, said at an announcement of its first-quarter results today that its revised 2015 capex will fall within a range of $10.5 billion and $11 billion.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
- 32Gbps SerDes IP in TSMC 12nm FFC
- 32Gbps SerDes IP in TSMC 22nm ULP
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related News
- U.S. to Hold Over 20% of Advanced Semiconductor Capacity by 2030, TSMC Expands Investment to US$165 Billion, Says TrendForce
- Arm Reports Quarterly Revenue of Over $1 Billion for First Time in Company’s History
- CSP CapEx to Soar Past US$520 Billion in 2026, Driven by GPU Procurement and ASIC Development
- IBM and U.S. Department of Commerce Announce America’s First Purpose-Built Quantum Foundry, Supported by Proposed $1 Billion CHIPS Award
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA