TSMC looks to standardise chiplet protocols in "world changing" move
By Nick Flaherty, eeNews Europe (October 9, 2023)
This is part of a move to the 3D Blox technology for building chiplet designs on the TSMC CoWoS process. The aim is to provide common data for chiplets from different silicon suppliers, substrate and PCB makers and the OSAT assembly and test companies.
“Today most of the chips except for the memories come from TSMC but the goal is to mix and match but that is still some way to go but we are trying to get there,” said Dan Kochpatcharin, head of Design Infrastructure at TSMC.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 3.3V Capable GPIO on TSMC 28nm RF HPC+
- 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- LDO Voltage Regulator, 250 mA, TSMC N3P
- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
Related News
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- Alphawave Semi Taped-Out Industry Leading 64Gbps UCIe™ IP on TSMC 3nm for the IP Ecosystem, Unleashing Next Generation of AI Chiplet Connectivity
- Alphawave Semi Delivers Cutting-Edge UCIe™ Chiplet IP on TSMC 3DFabric® Platform
- Standardization nears for next-generation Verilog <!-- verification -->
Latest News
- Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies
- aiMotive and Cadence Demonstrate Layer-by-Layer Workload Placement Across Independent AI Engines
- Alchip collaborates with Synopsys to Address Scale Up and Out Bandwidth Constraints
- M31 and Ambiq Collaborate on TSMC N12e® Foundation IP to Address Demanding SoC Power and Area Targets
- Siemens and TSMC advance AI-powered semiconductor design automation