UK startup unveils LTE transceiver IC
Peter Clarke, EETimes
4/4/2011 6:44 AM EDT
LONDON – Genasic Design Systems Ltd., a privately-held fabless RF design company formed in 2009, has announced the availability of its first chip, a 65-nm CMOS transceiver IC for HSPA and LTE applications.
The GEN4100 has dual receive and transmit chains enabling full MIMO operation in both transmit and receive. The company states that the IC has "low power consumption" making it suitable for use in handsets and dongles, as well as in 3G and 4G femtocell basestations. But the company does not quantify the power consumption. A data sheet is available on application the company states.
To read the full article, click here
Related Semiconductor IP
- LTE Turbo Decoder
- LTE Viterbi Decoder
- LTE Cat-1 bis (200 MHz – 2.5 GHz) wideband transceiver supporting TDD, FD-FDD, and HD-FDD operation—suitable for SDR implementations requiring flexible duplexing architecture.
- LTE Turbo Decoder
- LTE Release-9 UE PHY. (L1) IP
Related News
- Palma Ceia SemiDesign Announces Silicon-Proven LTE NB-IOT Transceiver for IoT Applications
- PCS Releases New 3GPP LTE Release 14-Compliant NB-IoT Transceiver IP Supporting High-Band and Low-Band Operation
- Palma Ceia SemiDesign Announces Silicon-Proven Dual Band LTE NB-IoT Transceiver for IoT Applications
- New Low-Pin, Hi-Speed USB transceiver interface endorsed by leading USB connectivity providers including ARC International, Conexant, Mentor Graphics, Philips, Standard Microsystems Corporation (SMSC), and TransDimension Inc.
Latest News
- Imec unlocks fourfold UWB range extension using world-first narrowband receiver chip compliant with IEEE 802.15.4ab standard
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology