SerDes signal integrity challenges at 28Gbps and beyond
Maintaining signal integrity has become increasingly difficult for SerDes designers at 28Gbps, 56Gbps and beyond. After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV).
With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization to correct. In addition, channel loss and reflections (noise) at increased data rates and noise complicate forward error correction.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Addressing Signal and Power Integrity for High-Speed Data Center Applications
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- How Big Is The Analogue/Mixed Signal Market?
- Mixed Signal Success Requires the Voice of Analog Designers
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car