sRAM generator HAUMEA at 90 nm on DOLPHIN Integration's website

Grenoble -- November 18, 2008 -- The winning performance mix BCD, Best for Consumption and Density, is heralded by the new sRAM Haumea generator at 90 nm LP process.

It represents the cornerstone of Dolphin Integration’s embedded memory strategy at a time when Foundry Pushed Rule bit-cells and the trap of "free libraries" stifle design creativity.

Haumea BCD can generate RAMS from 16 kbits to 512 kbits.

Until now it was not feasible to reach the best of two advantages at once: either a wide reach of generator "cuts", or a finely tuned memory instance. A new breed of compilers was needed and DOLPHIN Integration did it:

Haumea is indeed built from a pre-optimized interpolation compiler enabling at once the best dynamic consumption reduction and the best area with increased speed whatever the capacity targeted!

Not only this, but Haumea is unique in that its Read-Margin is automatically optimized for each instance:

Haumea indeed accounts for each specific configuration in terms of capacity and multiplexing, so as to guarantee maximum design yield in fabrication. This comes in contrast with fixing a unique Read-Margin or, even worse, letting the user set it at his own risk.

The 65 nm Haumea is coming soon.

With Haumea, cost reduction and low-power are neatly compatible!

Click here for more information on Haumea 90 nm

About Dolphin

Dolphin Integration is up to their charter as the most adaptive creator in Microelectronics to "enable mixed signal Systems-on-Chip", with a quality management stimulating reactivity for innovation.
Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.