CAST Improves SDIO Host and NAND Flash Memory Controller Cores
— Silicon Intellectual Property (IP) provider CAST, Inc. today announced improvements to two solid state memory (SSD) controller cores:
- The SDIO Host Controller Core available now adds support for high-capacity SD, SDIO, and MMC memory cards; includes built-in content protection and encryption; and features Open Chip Protocol (OCP) or AMBA interfaces. See www.cast-inc.com/cores/sdio-host for details.
-
An enhanced NAND Flash Memory Controller Core available next month includes 4-, 8-, and now 16-bit error correction with the Bose, Chaudhuri, and Hocquenghem (BCH) algorithm—critical for Multi Level Cell (MLC) memories—and features ONFi standard compliance and an OCP interface. See www.cast-inc.com/cores/nandflash-ctrl for details.
The new SDIO and NAND Flash controller cores were developed by long-time CAST partner Evatronix SA in Poland. They are part of CAST’s memory and storage controller IP family, which also includes DDR, DDR2, SDRAM, and ATE/IDE IP cores. The competitive speed, area, and low-power characteristics of these cores have made them suitable for a variety of customer applications, including aerial reconnaissance, cellular phones, mobile multimedia devices, and wireless sensors.
About CAST, Inc.
CAST provides a broad range of popular IP cores and system IP for ASICs and FPGAs. Privately owned and operating since 1993, CAST has a reputation for high-quality IP products and industry-leading technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia. Learn more at www.cast-inc.com.
Related Semiconductor IP
- SDIO Host Controller IIP
- SDIO Device Controller IIP
- SDIO Slave Controller
- SD / SDIO / MMC Host Controller
- SDIO to UART Controller
Related News
- Arasan Demonstrates World's First SD / SDIO Host Ver 2.00 IP Core with Advanced DMA
- Evatronix upgrades its SDIO Host Controller with the full support for CPRM, MMC 4.2, and SDIO specification rev. 2.0.
- Sierra Wireless licenses Arasan Chip System's SDIO Host controller IP core
- Aizyc announces silicon proven SDIO 3.0 Host IP Core
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack