Qualis©Releases 10G Ethernet and PCI-X Domain Verification Components for OpenVera

Latest extension to the Qualis DVC platform offers a 10x to 25x productivity increase for verification of 10 Gigabit Ethernet and PCI-X designs

LAKE OSWEGO, Oregon, April 16, 2002 - Qualis Design Corporation, the independent leader in advanced verification methodologies, announces the availability of powerful new Verification Components for Synopsys (NASDAQ:SNPS) OpenVera that dramatically reduces the verification time of complex Gigabit Ethernet-based networking and PCI-X-based products. Based on Qualis' advanced plug-and-play Domain Verification Component^TM (DVC^TM) architecture and verification platform, the new components allow verification engineers to quickly build Gigabit Ethernet and PCI-X based verification environments that leverage the power of OpenVera and advanced verification methodologies.

"Our new 10 Gigabit Ethernet DVC enhances our offering of advanced Ethernet verification solutions for OpenVera," said Michael Horne, president and CEO of Qualis. "Now verification engineers can tap into the full power of VERA and advanced verification methodologies for Ethernet applications supporting 10 Megabit, 100 Megabit, 1 Gigabit and 10 Gigabit industry standards. This offering sets the standard in verification support, capability, and quality."

The 10 Gigabit Ethernet DVC is a complete test environment supporting the IEEE P802.3ae/D4 draft specification for 10 Gigabit Ethernet, offering highly-programmable and extendable stimulus generation, automated response checking, and test coverage measurement. The new DVC provides an easy interface for generating test packets for the XGMII and XAUI MAC-layer and PHY-layer physical interfaces, detecting error conditions, catching protocol violations, and checking for compliancy to the industry draft standard.

The PCI-X DVC is the newest offering in Qualis' family of DVCs for support of Core Interconnect protocols and interfaces. The new DVC is a complete test environment supporting the PCI Local Bus Specification revision 2.2 and the PCI-X addendum, revision 1.0a, including full random, constrained random, and directed transaction generation and response, corruption and analysis. Supporting both bus master and slave functions, the PCI-X DVC provides complete bus monitoring, injection of random physical and logical errors, protocol checking, functional coverage, and generic transaction scoreboarding. A single PCI-X DVC supports the verification of an unlimited number of PCI-X master or slave devices.

"With their knowledge of advanced verification methodologies and domain-specific protocols and interfaces, Qualis is well positioned to deliver solid solutions that break the verification bottleneck," said Dennis Shwed, vice president of hardware development at S2IO Technologies. "This new DVC technology promises to help accelerate verification schedules and speed the adoption of VERA." S2IO Technologies develops advanced 10 Gigabit compute server and mass storage I/O solutions.

Both the 10 Gigabit Ethernet and PCI-X DVCs are much more than simple simulation models. The new technology embeds protocol knowledge and advanced verification techniques in easy-to-use reusable blocks. Both DVCs dramatically raise the level of productivity of verification engineers by providing pre-verified stimulus generation and automated response checking components that leverage the power of Synopsys' VERA^© testbench language simulator. Verification engineers can quickly assemble a verification environment for complex Ethernet and PCI-X designs and immediately focus on their primary goal: writing testbenches that verify their design.

10G Ethernet DVC supports emerging standard
The new 10 Gigabit Ethernet DVC enhances the features found in the 10/100/1G Ethernet DVC available from Qualis, and offers a rich set of features, including:

IEEE P802.3ae/D4 draft specification compliant, comprehensive test environment. Configurable for verifying a system of any number of XGMII and XAUI MAC-layer and PHY-layer physical interfaces.
Full integration with Qualis 10/100/1G Ethernet DVC (see http://www.qualis.com/dvc.ethernet.vera.pdf for more information)
Leverages the full power of the Synopsys VERA testbench tool. Full support of SoC/ASIC, FPGA, system, and board-level verification
Full support of automatic random, constrained random, and directed testcase creation
Built-in flexible checking mechanism, with on-the-fly protocol checkers/monitors and coverage support
Extendable architecture allows user to create standalone test environment or embed the DVC in a larger existing test environment
Supports IEEE 802.2 LCC/SNAP tagging; IEEE802.1Q VLAN tagging, control frames for PAUSE operations; promiscuous and multicast modes
Supports MAC frame generation, corruption, and analysis; generic MAC frame scoreboarding
Full compatibility with Qualis DVC family for multi-protocol, multi-domain verification

For a complete listing of features of the 10 Gigabit Ethernet DVC for OpenVera, visit our website at http://www.qualis.com/dvc.10g.vera.pdf.

PCI-X DVC for Core Interconnect
The new PCI-X DVC offers a rich set of features, including:

PCI Local Bus Specification revision 2.2 and PCI-X addendum revision 1.0a compliant, comprehensive test environment. Configurable for verifying a system of any number of PCI-X bus masters or slaves
Leverages the full power of the VERA testbench tool. Full support of SoC/ASIC, FPGA, system, and board-level verification
Full support of automatic random, constrained random, and directed transaction generation and response, corruption and analysis
Extendable architecture allows user to create standalone test environment or embed the DVC in a larger existing test environment
Complete bus monitoring support for bus masters and slaves
Supports injection of random physical and logical errors
Supports protocol checking, functional coverage, and generic transaction scoreboarding

For a complete listing of features of the PCI-X DVC for OpenVera, visit our website at http://www.qualis.com/dvc.pcix.vera.pdf.

Pricing and availability
The 10 Gigabit Ethernet and PCI-X DVCs are available in June 2002, with beta-release access available today for select customers. All Qualis DVCs support interfacing to Verilog and VHDL designs. Annual licenses are priced at $US 15,000 each, with volume discounts available for customers who run large regression simulations. All DVCs for OpenVera and Specman come with full documentation and example configurations for typical verification environments. Qualis also offers full methodology training and support services for its DVCs, including its QuickRamp^TM family of DVC deployment solutions. For more information, visit at http://www.qualis.com/dvc.html.

About Qualis Design Qualis Design is the leading independent verification methodology company offering a rich selection of productivity enhancing Domain Verification Components (DVCs), methodology consulting, and best-in-class training services. By leveraging its deep experience in verifying networking, processor/SoC, and wireless products, Qualis creates verification product solutions that solve the most challenging functional verification problems in the world. Users of Qualis' revolutionary technology and verification methodology know-how build sustainable competitive advantages that keep them on the edge. Qualis is headquartered in Lake Oswego, Oregon and has development centers in Ottawa Ontario Canada, and Grenoble, France. To learn more, visit http://www.qualis.com/.

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