Jumpstart your Hardware Validation with QuickPlay at DAC 2015
SAN FRANCISCO, Calif., May 28, 2015 -- PLDA will privately showcase QuickPlay, a Virtualized Hardware Validation Platform at DAC 2015. QuickPlay accelerates hardware development by enabling fast and early-on hardware validation of HDL Blocks with large real world, real time datasets with a cost effective instant-on platform. Its ease of implementation also enables the creation of automatic regression tests to streamline the validation process even further.
QuickPlay is already in used by several Early Access Customers, and PLDA is leveraging the DAC event to expand its Early Access Program to a wider audience. Following a staged rollout strategy, the QuickPlay team is offering 30mn private tours of its platform and interested customers can register on the QuickPlay web page to reserve their slot to see QuickPlay in action and discuss their Hardware Validation needs and challenges with the QuickPlay team.
For more information about QuickPlay, please visit https://www.plda.com/quickplay-4-hw-validation and set up an appointment with the QuickPlay team.
About PLDA
PLDA is a 18+ year old private company recognized for its leadership and expertise in FPGA/ASIC IPs, FPGA-based Boards/SOM and Design Tools. With over 5,800 licenses, PLDA has establish a vast customer base and the world’s broadest PCIe ecosystem. Its expertise and award winning support has made PLDA a unique supplier of IPs, FPGA-based boards, API’s and Tools supplying its products to the biggest names in all market segments, from the largest Semiconductor Companies to Military and Financial institutions. PLDA is a global company with offices in North America (San Jose, California) and Europe (France, Italy, Bulgaria).
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- PLDA Announces "Inspector" - An Evolution of the PCI Express 4.0 PDK That Enables PCIe 4.0 Technology Design Validation and Performance Optimization Today
- PLDA Announces vDMA, a Highly Efficient Many-Channel DMA Engine Engineered for Virtualized Systems in Data Centers, to be demonstrated at Flash Memory Summit 2017
- PLDA Announces New Test And Validation Platforms For PCIe
- Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre Silicon Hardware Debug and Software Validation
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers