Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs
WILSONVILLE, Ore., June 3, 2013 —Mentor Graphics Corp. (NASDAQ: MENT) today announced that cache coherent interconnect subsystem verification has been added to the Questa® and Veloce® platforms. Engineering teams designing high-performance, distributed computing systems with ARM’s AMBA 5 CHI specification, or mobile applications devices with ARM’s AMBA 4 ACE specification, can now fully verify that the interconnect subsystems achieve maximum system-level performance and the distributed cache memories are coherent.
“Many teams in multi-core SoC design are moving to coherent interconnect architectures to gain a competitive advantage,” said Andy Nightingale, director, System IP Marketing, ARM. “We’re pleased that our collaboration with Mentor is providing verification platforms to facilitate the deployment of our mutual customers’ next-generation ARM-based solutions. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms.”
“Mentor’s multi-core, cache-coherent solution goes beyond traditional interconnect verification alternatives,” said Mark Olen, DVT division verification solutions manager, Mentor. “The Questa platform combines dynamic simulation, static formal, and system-level verification IP to fully verify cache coherent interconnect subsystem connectivity, functionality, and performance. The Veloce platform then lets engineers scale their environments and verify their coherent interconnect subsystems within the context of an entire system, including software.”
Engineering teams designing SoCs with ARM’s AMBA 5 CHI specification or AMBA 4 ACE specification want their products to achieve maximum performance with minimum power consumption. The Mentor® new multi-core, cache-coherent verification solution enables engineers to ensure that system-level designs are optimized to take the fullest advantage of either architecture. It confirms system-level protocol adherence and efficient cache coherency, as well as interconnect dynamic connectivity and performance.
The Questa and Veloce platform AMBA 4 ACE verification solutions are available immediately. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees. Contact your local Mentor Graphics representative for pricing details.
About Mentor Graphics
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Mentor's Questa and Veloce platforms help SimpleMachines dramatically speed development of its first AI processor
- Mentor Graphics Veloce Power Application Redefines Power Analysis Flow
- Mentor Graphics Veloce VirtuaLAB Adds Next-Generation Protocols for Leading-edge Networking Designs
- Mentor Graphics Veloce Emulation Platform Supports Andes Processors
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack