Innovium Adopts the Cadence Innovus Implementation System for Its Highly Scalable Switch Silicon Family for Data Centers
SAN JOSE, Calif., 18 Jul 2019 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Innovium, a leading provider of innovative data center switching silicon solutions, has adopted the Cadence® Innovus™ Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centers. For more information on the Cadence Innovus Implementation System, please visit www.cadence.com/go/innovusics.
The size and complexity of the highly innovative Innovium designs require high-capacity, fast and accurate design tools for advanced-node design implementation. The Cadence Innovus Implementation System provides Innovium with the following benefits:
- Massively parallel architecture: Lets Innovium handle large design sizes with multi-threading on multi-core workstations and distributed processing over networks of computers.
- GigaPlace™ solver-based placement technology: Provides Innovium with a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes.
- Multi-threaded, layer-aware optimization engine: Enables Innovium to reduce dynamic and leakage power with the engine’s timing- and power-driven capabilities. With the comprehensive power reduction techniques inside the Innovus Implementation System, Innovium reduced power consumption by the end of the implementation stage to within 2% of final signoff power.
- Core engine technologies: Offers Innovium access to innovative implementation technologies for FinFET process nodes such as IR-aware placement, clock skewing for power, continuous congestion monitoring and optimized routers for handling self-aligned double patterning, meeting power, performance and area (PPA) goals.
“Our highly skilled engineering team is always pushing the limits of massive, advanced-node SoC designs, and the Cadence Innovus Implementation System enabled us to achieve our PPA goals and overall engineering productivity so we can deliver our innovative and high-performance designs to market within aggressive timelines”, said Keith Ring, vice president of technology at Innovium.
The Innovus Implementation System is part of the broader Cadence digital and signoff suite, which provides customers with an integrated full flow, delivering a predictable path to design closure. It supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time
- Freescale Speeds SoC Implementation Time by 7X with Cadence Innovus Implementation System
- TSMC Certifies Cadence Innovus Implementation System on 16-nanometer FinFET Plus Process
- HiSilicon Adopts Cadence Innovus Implementation System for Production DSP Designs
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack