Faraday Introduces UrLib+ Add-on Library on UMC 40LP Process
Hsinchu, Taiwan -- May. 16, 2017 -- Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today introduced its new UrLib+™ add-on library for the third-party library on UMC 40LP process technology. UrLib+ is a library package, featuring extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, clock tree noise reduction, robust ESD protection, and lower ECO cost over the traditional physical libraries.
By utilizing Faraday’s 24-year experiences in library development and ASIC implementation, UrLib+ can be seamlessly integrated with the existing third-party library on UMC 40LP process to improve the routing results and yield for mass production. With UrLib+ supported, the CPU core can save around 43% of clock tree power and up to 15% of total power. For the routability efficiency, UrLib+ can shrink the die size from 4% to 11% depending on the design architecture and cell mapping flow. UrLib+ solution is not only dedicated for 40LP, Faraday also supports UrLib+ porting service for other third-party libraries or technology platforms.
“Library design is the foundation of IC design. Driven by ASIC product diversification, Faraday always has unique ideas and practices in library design,” said Steve Wang, President of Faraday. “In the UMC's advanced processes, the continuous realization of the library improvements is our persistent goal. We believe UrLib+ is a win-win-win solution for IC design house, fab, and third-party library vendor.”
About Faraday Technology Corporation
Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, covering the U.S., Japan, Europe, and China. For more information, please visit:www.faraday-tech.com .
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Faraday Releases Licensable Gigabit Ethernet PHY on UMC 40LP Platform
- Faraday Unveils Complete Imaging and Display High-Speed Interface IP Set on UMC 28nm and 40nm Processes
- Faraday Announces 16G Programmable SerDes in UMC 28HPC+
- Faraday Unveils SONOS eFlash Platform with Infineon on UMC 40uLP
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack