Silicon IP Provider, Chips&Media Unveils New Multi Video Codec IP, WAVE6 Gen2+

Seoul, South Korea --Oct 23, 2024 — Chips&Media (C&M), a global leader in video codec IP and application-specific NPU IP, today announced the WAVE6 Gen2+ series, a new multi-standard video codec hardware IP based on the next-generation video codec IP platform WAVE6.

The WAVE6 Gen2+ series is a newly designed IP series that leverages the comprehensive architecture to deliver advanced performance and high-quality images. The architecture has been upgraded to support higher bandwidth efficiency, minimum area size, and low latency. Additionally, the visual quality has been significantly improved compared to the earlier released WAVE6 series, as measured by PSNR and SSIM metrics. These improvements were achieved by optimizing primary encoding factors and algorithms that directly impact quality.

WAVE6 Gen2+ series is the performance-enhanced single-core version of the WAVE6 series, targeting 8K30fps with a 550MHz core clock (500MHz for the decoder). Its size is expected to be between the WAVE6 single-core and dual-core versions.

It supports all video codecs of the WAVE6 series—HEVC, AVC, and AV1— including the VP9 decoder. VVC and AV2 decoders will be added later.

The Gen2+ series features its small, embedded processor that manages HOST commands, requiring an extremely low HOST CPU load. The C&M’s VPU (Video Process Unit) operates in two clock domains for practical synthesis and performance: one for the video engine core and the other for the entropy engine.

To save bandwidth, the architecture uses C&M's proprietary frame buffer compression (CFrame10TM) for reference frames. This can allow bandwidth efficiency to improve by 5-10% from the WAVE6 series. For 8K30p, YUV420, and IBBP GOP, the estimated bandwidth is 8-bit.

In terms of area, the WAVE637DV Gen2+ is estimated to be two-thirds of the WAVE6 dual-core version.

Power consumption has also been improved through higher clock-gating ratio/efficiency and more detailed clock-gating. C&M’s power estimation tools help optimize power consumption, and the architecture supports a more detailed clock distribution scheme for clock gating and power control.

The Gen2+ series supports third-party frame compression (AFBC, PVRIC) for source and output images. It also offers variable rate control for the encoder, which is FixedQP/CBR/VBR/CVBR, Frame level & CU level rate control, and a Custom map feature.

This series’ encoding image quality is better than that of the WAVE6 series. It supports on-the-fly pre-processor features such as Rotation/Mirror (exclusive with other pre-processing), color space conversion (RGB-to-YUV), 422/444 to 420 format conversion, bit depth conversion, crop, and sub-frame sync (ultralow-delay encoding I/F). Additionally, it offers on-the-fly post-processor features like down scaler (~1/8), color space conversion (YUV-to-RGB), 422 to 420 format conversion, bit depth conversion, and crop.

It also features PX4, which supports YUV420, YUV422, and YUV444 encoding/decoding for AV1, HEVC, and AVC. It can also support VP9 profile0/2 decoding (YUV420 only).

This new IP, Gen2+ series, is an ideal solution for advanced technologies and vision-based applications, including consumer electronics, automotive, surveillance cameras, and more.

Overall Description

Supported Standards

Value-added

• Color space conversion (RGB-to-YUV, YUV-to-RGB)
• 422/444 to 420 format conversion
• Down-scaler (~1/8)
• 3-party interface
• Rotation/Mirror (Exclusive with other pre-processing)
• Bit depth conversion
• Crop
• Sub-frame sync (ultra low-delay encoding I/F)

About Chips&Media

Chips&Media provides ultra-low-power, high-performance multi-codec video IPs to semiconductor companies internationally. It specializes in video codec IPs and image-quality-enhancing specific NPU IPs for the surveillance, automotive, and broader consumer electronic markets. The company was founded in 2003 and is headquartered in Seoul, South Korea, with offices worldwide.

Visit www.chipsnmedia.com for more information.