Chelsio Adopts Synopsys DesignWare 56G Ethernet PHY IP to Accelerate Development of High-Performance Computing SoC

Silicon-Proven 56G Ethernet PHY Delivers True Long Reach Performance with Flexible Data Rates and Low Latency

MOUNTAIN VIEW, Calif., Aug. 27, 2020 -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Chelsio has adopted its silicon-proven DesignWare® 56G Ethernet PHY IP to accelerate development of Chelsio's System-on-Chip (SoC) design targeting high-performance smart network interface card (NIC) and server applications. Chelsio selected the Synopsys DesignWare 56G Ethernet PHY IP due to its support for a wide range of data rates from 1.25 Gbps to 56 Gbps across standards such as Ethernet, PCI Express, OIF, and JESD. The DesignWare 56G Ethernet PHY with firmware-controlled algorithms including continuous calibration and adaptation (CCA) delivers robust performance across a range of voltage and temperature variations.

The Ethernet verification IP and source code test suites enable the design and verification of SoCs with ease-of-use and optimum performance, resulting in accelerated verification closure. To speed development of high-performance computing SoCs, Synopsys provides companies like Chelsio with the industry's most comprehensive IP solutions, including 56G and 112G Ethernet PHYs, DDR5, PCI Express 5.0, die-to-die USR/XSR and HBI PHYs, Compute Express Link (CXL), and CCIX.

"Our next-generation high-speed Ethernet interconnect SoCs used for networking and storage in hyperscale data centers, required mature IP solutions with a flexible and scalable architecture," said Kianoosh Naghshineh, CEO, Chelsio Communications. "After an extensive evaluation process, we chose Synopsys' silicon-proven DesignWare 56G Ethernet PHY IP because it gives us the most reliable reach and performance advantages we needed to meet our high-performance design requirements."

"The significant growth in cloud computing workloads is driving new SoC architectures for compute, storage, and networking applications," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "By providing designers with most essential and trusted IP for high-performance computing SoCs, Synopsys is helping companies such as Chelsio address the performance, latency and memory requirements of their designs and quickly get their products to market."

Availability and Additional Resources
The DesignWare 56G Ethernet PHY IP is available now. For more information, visit the DesignWare 56G Ethernet PHY IP and High-Speed SerDes PHY IP web pages.

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.