Cadence Innovus Implementation System Qualified on Samsung 10nm FinFET Process
Enables systems and semiconductor companies to deliver advanced-node designs to market faster
SAN JOSE, Calif., 16 Feb 2016 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Innovus™ Implementation System has been qualified for Samsung Foundry’s latest 10-nanometer (10nm) process. The Innovus Implementation System is a next-generation physical implementation tool with integrated signoff engines that have been validated for Samsung designs, providing customers with the fastest path to implementation and closure and optimal power, performance and area (PPA).
The Innovus Implementation System offers customers key technologies for using the Samsung 10nm process including the GigaPlace™ solver-based placement technology, a slack-driven, pin access-aware placer that improves electrical and physical design convergence at advanced nodes. The tool also offers integration with the Cadence Quantus™ QRC Extraction Solution, the Tempus™ Timing Signoff Solution, the Voltus™ Power Integrity Solution and the Physical Verification System, all of which enable design convergence for faster design closure. The Innovus Implementation System incorporates a massively parallel architecture that increases capacity and drives better turnaround time without compromising PPA. For more information on the Innovus Implementation System, please visit www.cadence.com/innovus.
“We have collaborated with Samsung to enable customers to deploy production flows on 10nm FinFET designs in order to achieve the best PPA and overcome design complexity to meet aggressive time-to-market demands,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “We are actively working with customers on new designs on the Samsung 10nm process using the Innovus Implementation System, and we are seeing early successes that can enable these designers to stay in front of the competition.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- TSMC Certifies Synopsys IC Compiler II for 10-nm FinFET Production and 7-nm Early Design Starts
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- Silicon Creations Taps Silvaco's Custom Design Flow for 10nm FinFET Designs
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
Latest News
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Arm Announces Appointment of Eric Hayes as Executive Vice President, Operations