Blue Pearl Software Visual Verification Suite 2016.2 Simplifies ASIC, FPGA and IP RTL Verification
New Management Dash Board tool along with enhanced Lint, Debug and Clock Domain Crossing flows accelerate RTL Verification
Santa Clara, CA -- June 01, 2016 -- Blue Pearl Software, Inc. a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite 2016.2. The release adds a new Management Dash Board tool for improved visibility and accountability during RTL verification, along with enhanced waiver management and Tcl-based flows accelerating RTL verification times.
The Management Dash Board tool is architected to address the age old problem; one can’t manage what one can’t measure. This standalone option to the Visual Verification Suite provides real-time visibility into RTL verification progress, run to run, providing graphical project reports customized for documentation and design reviews, highlighting coverage, errors, warning and waivers for both Analyze RTL Linting and Clock Domain Crossing (CDC) solutions.
“Blue Pearl Software delivers innovative solutions that provide the industry’s fastest bug find / fix rate for RTL analysis and debug, CDC and timing constraints generation,” said Ellis Smith, Chairman and CEO, Blue Pearl Software. “Management in our key customers have been asking for improved visibility to better assess schedules, risk and quality of their designs. The new Management Dash Board fills this request.”
Also in this release, is a new XML-file based waiver manager for faster creation and management of messages and CDC waivers designed to streamline the debug and analysis and an enhanced Tcl-based flow for batch mode debug on both Windows and Linux platforms.
To Learn More
Visual Verification Suite 2016.2 will be demonstrated at the Design Automation Conference (DAC), June 6-9th, in Booth #929, Austin Convention Center, Austin, Texas. To reserve a private demo at DAC, please register here or visit http://www.bluepearlsoftware.com.
For more information on how you can accelerate your RTL Verification with Visual Verification Suite and talk to a local sales representative visit http://www.bluepearlsoftware.com.
About Blue Pearl Software
Blue Pearl Software, Inc. is a provider of DO-254 complaint design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies, who wish to avoid costly and time consuming design spins due to simulation / HW mismatches, invalid constraints and clocking issues.
Visit Blue Pearl Software at http://www.bluepearlsoftware.com
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Toshiba Information Systems Adopts Blue Pearl Software Visual Verification Suite by to Improve Quality and Accelerate FPGA and ASIC Development
- Blue Pearl Software and NanoXplore SAS team to Accelerate Development and Verification of Radiation Hardened FPGA Designs
- Blue Pearl Adds Design Verification and Methodology Services to its Product Portfolio
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers