Arteris Adds Support for ARM AMBA 5 AHB5 Protocol
ARM TechCon 2016, SANTA CLARA, Calif. — Oct. 25, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has implemented ARM® AMBA® 5 Advanced High-Performance Bus 5 (AHB5) protocol support in its FlexNoC Interconnect IP and Ncore Interconnect IP products.
The AHB5 specification is an update to the previous ARM AMBA 3 AHB specification. It provides support for the ARMv8-M architecture, adding features that extend ARM TrustZone® technology support throughout the SoC.
“ARM and its rich ecosystem enable rapid deployment of complete solutions for secure smart embedded devices and accelerating delivery to market,” said Nandan Nayampally, vice president of marketing and strategy, CPU group, ARM. “Arteris’ support of AHB5 is another demonstration of how ARM’s ecosystem helps to simplify and foster the development of secure Internet of Things devices.”
“Arteris has been an enthusiastic supporter of ARM AMBA specifications since our inception, implementing the ARM AMBA 3, 4 and 5 specifications within our interconnect IP products,” said K. Charles Janac, President and CEO of Arteris. “We are strongly committed to supporting the advancement of ARM interconnect standards on a long-term basis to enable semiconductor design teams to more easily create SoCs using IP from the ARM ecosystem.”
About Arteris
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / Hisilicon, Mobileye, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at www.arteris.com.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
Related News
- Cadence Announces Verification IP for ARM AMBA 5 AHB5
- Silistix Self-Timed Interconnect Solution Supports AMBA Bus Protocol
- Sonics Offers Free Evaluation for Designers of Sonics Network for AMBA Protocol Solution
- Sonics Network for AMBA Protocol Now Available for Windows
Latest News
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems
- QuickLogic Appoints Quantum Leap Solutions as Authorized Sales Representative
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud