Algo-Logic Systems Launches 40Gbps TCP Endpoint on BittWare S5-PCIe-HQ FPGA Board
The high throughput 40G TCP Endpoint delivers an ultra-low-latency of 96.0 nanoseconds
SANTA CLARA, Calif. -- June 17, 2015 -- Algo-Logic Systems, a recognized leader in providing hardware-accelerated, deterministic, ultra-low-latency products, systems and solutions for accelerated finance, datacenter acceleration, and embedded system industries, today announced availability of their new 5th Generation 40G TCP Endpoint running on Bittware's S5-PCIe-HQ platform. The IP-Core enables FPGA-implemented logic to directly communicate over 40 Gigabit Ethernet networks with remote hardware or software devices and includes easy to use hardware application programming interface that supports multiple real-world accelerated datacenter use cases.
Their network-tested 40G TCP Endpoint delivers ultra-low-latency of 96.0 nanoseconds at full duplex rates of 80 Gbps. This 40G TCP Endpoint IP-Core solution runs on the Altera Stratix V FPGA on BittWare's S5-PCIe-HQ full height, half-length platform with dual QSFP+ ports. Designed for high-end applications, the Stratix V provides a high level of system integration and flexibility for I/O, routing, and processing. Over 16 GBytes of on-board memory includes DDR3 and QDRII/II+. Two front-panel QSFP+ cages allow two 40GigE interfaces (or eight 10GigE) direct to the FPGA for reduced latency, making the board ideal for high frequency trading and networking applications. The S5PH-Q also features a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management. All of these features combine to make the S5PH-Q a versatile and efficient solution for creating and deploying high-performance FPGA computing systems for Network Packet Processing and High Performance Computing applications in financial services, MAG (military, aerospace, and government), and instrumentation.
Each instance of the core supports up to 512 sessions of TCP traffic. However, unlike a software TCP endpoint, Algo-Logic's FPGA TCP Endpoint enables a single session to send traffic at rates up to 40 Gbps in datacenters where round-trip latency is low. Additionally, it supports aggregate traffic flows that add to 40 Gbps for multiple sessions running over higher latency networks. The TCP Offload Engine (TOE) configurations are specifically designed for real-world datacenter acceleration and commercial deployment scenarios. The key features of the 40G TCP Endpoint include:
- Allows scaling from a single TCP session running at 40 Gbps up to 512 sessions per 40G port
- Utilizes a small logic footprint of under 5.0% ALMs in a Stratix V A7 FPGA
- Operates at full 40GE line rate (80 Gbps duplex) on platforms with dual QSFP+ links
- Provides very high throughput with small and large payloads including jumbo frames
- Delivers reliable delivery of data directly between FPGA accelerators and host machines
Algo-Logic's 40G TCP Endpoint can be seamlessly integrated with other components of Algo-Logic's Gateware Defined Networking® (GDN) IP-Core libraries, such as the Key Value Store (KVS) in-memory database, as well as with customer applications that perform N-Tuple packet classification and Network Functional Virtualization (NFV).
"BittWare's FPGA boards offer tremendous processing capabilities to datacenters and data streaming applications, but for some users it can be a challenge to leverage those capabilities without application building block IP libraries," said Ron Huizen, VP of Systems and Solutions at BittWare, Inc., "We are excited that with this release of their new 40G TCP Endpoint, Algo-Logic Systems now allows users to handle those challenges with a complete library of network processing application IP-Cores that can address ingress, egress, and almost everything in between."
"We are pleased to collaborate with BittWare to jointly launch our industry-first 40 Gbps TCP Endpoint on their leading FPGA Platform," said Imran Khan, VP of Marketing and Business Development at Algo-Logic Systems, Inc., "This TCP platform solution will enable both high throughput and network traffic acceleration with the lowest latency in datacenters."
Algo-Logic's world-class hardware-accelerated systems and solutions are used by datacenter operators to increase throughput, minimize latency, and reduce both capital and operating expenses.
Price and availability
For additional information, please contact Info@algo-logic.com or visit Algo-Logic's website at: http://www.algo-logic.com
About BittWare, Inc.
For over 25 years, BittWare has designed and deployed high-end signal processing, network packet processing, and high performance computing board-level solutions that significantly reduce technology risk and time-to-revenue for our OEM customers. Our products are exclusively based on the latest FPGA technology from Altera and industry-standard COTS form factors including PCIe, VPX / OpenVPX, AMC, XMC and FMC (VITA 57). When customer requirements make it difficult to use industry-standard boards, BittWare can provide modified solutions, and/or licensed designs for applications in the financial services, broadcast, instrumentation, compute & storage and MAG (military, aerospace, and government) markets. For more information on BittWare and its innovative FPGA platform solutions, visit www.bittware.com.
About Algo-Logic Systems
Algo-Logic Systems, Inc., is a recognized leader and developer of fast time-to-market gateware libraries for Field Programmable Gate Array (FPGA) devices. Algo-Logic IP-Cores are used to lower latency in trading systems, increase packet throughput in datacenters, and lower power for data processing in embedded systems.
Related Semiconductor IP
Related News
- Algo-Logic Systems Launches Industry-First 40Gbps TCP Endpoint on Altera Stratix V for Datacenter Acceleration
- Algo-Logic Systems Launches 40Gbps TCP Endpoint on ReFLEX XpressGX5-LP FPGA Board
- Algo-Logic Systems 3rd Generation TCP Endpoint Achieves Ultra-low-latency of 76-nanoseconds on Stratix V FPGA
- Intilop's 76-nanosecond full TCP Offload (TOE) establishes yet another System Latency record with Altera Stratix-V FPGA board from BittWare
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers