Airoha Technology Adopts Cadence RTL Synthesis and Test Solution, Reducing Power Consumption by 15 Percent
Encounter RTL Compiler and Encounter Test also reduced test pattern count by 10 percent on Bluetooth wireless radio chip
SAN JOSE, Calif. -- Jul 30, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Airoha Technology Corp. adopted the Cadence® Encounter® RTL Compiler and Cadence Encounter Test solutions after a rigorous competitive evaluation, and achieved a 15 percent reduction in power consumption and 10 percent reduction in test pattern count on a Bluetooth wireless radio chip. Encounter RTL Compiler employs unique global mapping technology and advanced clock gating to reduce power consumption without compromising design performance goals.
Airoha also deployed the Cadence Encounter Conformal® Equivalence Checker and the Cadence Encounter Digital Implementation System on this chip. The full integration of Encounter RTL Compiler, Encounter Test and Conformal Equivalence Checker allowed Airoha to easily migrate from their existing flow to a more holistic front-end logic design environment.
“Cadence offers a well integrated solution, and takes almost no efforts to migrate. We were able to transfer an entire third-party synthesis flow over to Encounter RTL Compiler within just one day, saving time and allowing uninterrupted production for the engineering team,” said Dr. David Chang, president and CEO of Airoha. “With this Cadence solution, we were able to provide the highest quality of silicon, faster time to market and more low power than would have been possible with our previous flow.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related News
- Mentor Graphics Announces Precision RTL Plus for FPGA Synthesis -- Vendor-Independent Solution for Breakthrough Productivity
- BDTI Certified Results Show PICO High Level Synthesis Platform Produces Quality of Results Comparable to Hand-coded RTL
- Jasper Releases Two Property Synthesis Apps Targeted at Early RTL Qualification and Coverage-Driven RTL Verification
- Mentor Graphics Acquires Oasys RealTime to Bring RTL Synthesis to its Digital Implementation Flow
Latest News
- ASICLAND Partners with Daegu Metropolitan City to Advance Demonstration and Commercialization of Korean AI Semiconductors
- SEALSQ and Lattice Collaborate to Deliver Unified TPM-FPGA Architecture for Post-Quantum Security
- SEMIFIVE Partners with Niobium to Develop FHE Accelerator, Driving U.S. Market Expansion
- TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs
- Efficient Computer Raises $60 Million to Advance Energy-Efficient General-Purpose Processors for AI