intoPIX delivers new JPEG2000 RAW FPGA IP-cores to compress Camera Bayer pattern-images 2013-09-10 07:45:00 IP Cores & Design
Cadence Launches Palladium XP II Verification Platform and Enhanced System Development Suite 2013-09-10 06:52:00 EDA & Design Tools
Soitec licencing to TSMC its IP portfolio related to back-side illumination technology for image sensors 2013-09-10 03:58:00 Foundries & Process Nodes
Mentor and ASSET Deliver IJTAG Automated Chip-to-System-Level IP Integration 2013-09-09 15:46:00 EDA & Design Tools
Synopsys Announces DFTMAX Ultra to Significantly Reduce Silicon Test Costs 2013-09-09 15:08:00 EDA & Design Tools
Synopsys Announces DesignWare STAR Hierarchical System to Accelerate Silicon Testing of SoCs 2013-09-09 15:06:00 IP Cores & Design
Dialog Semiconductor Licenses Cadence's Industry-Leading Tensilica Hifi Audio/Voice DSP IP 2013-09-09 09:10:00 Commercial Deals
PRO DESIGN Releases FMC Adapter Kit for Its proFPGA Virtex 7 Based FPGA/ASIC Prototyping Solution 2013-09-09 08:31:00 Misc
TSMC and Synopsys Extend Custom Design Collaboration into 16-nm 2013-09-09 07:33:00 EDA & Design Tools
Open-Silicon Improves Test Quality with Mentor Graphics Tessent Cell-Aware Test 2013-09-09 03:44:00 EDA & Design Tools
Barco Silex releases Multi-Channel Ultra HDTV 8K JPEG 2000 encoder and decoder cores 2013-09-06 11:13:00 IP Cores & Design