Aliathon announces 100G Transponder & Muxponder Demo Design
April 5, 2012 -- Aliathon announces the immediate availability of our 100G OTN dual Transponder / Muxponder demo design recently demonstrated to customers at OFC 2012.
This demo design platform has been engineered to give our clients an easy-to-use, flexible and feature-rich experience that accelerates their product introduction in to the 100G OTN market. The design is available for evaluation in both the Aliathon and Xilinx engineering labs.
Headline Features
- Compliant to ITU G.709 Standard.
- Architected to fit comfortably inside a single-chip FPGA .
- 200MHz+ Push Button Core Performance.
- Scales to Future OTN Rates (n x 100G, 400G).
- CAUI Client / OTL4.10 Line Side Interfaces.
- 100GE & 10G clients Mapped in to OTU4 Payload via GMP.
- 100G & 10G Framing & Section/Path OH Processing.
- Support for generic G.709 FEC.
- 7db NECG @ 6.7% OH G.709 Standard GFEC.
- 100G Transponderare delighted to Demo Design Product Brief
- 100G Muxponder Demo Design Product Brief
Target Applications.
Target applications include 100GE long-haul transport and metro / router network aggregation.
Later in 2012 Aliathon will be rolling out our other 100G reference design platforms. See below the basic architectures of these solutions.
- 100G Regenerator/Repeater.
- Interlaken - OTU4 Transponder.
Related Semiconductor IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
Related News
- Altera's Stratix IV GT FPGA Selected by NEC for Use in Advanced 100G Transponder Card for DWDM System
- Avalon and AppliedMicro Enable Efficient 100G Muxponder Applications
- Aliathon Ltd. Announces the immediate availability of their 100G OTN Transponder Reference Design For XILINX FPGAs.
- Altera's Stratix V FPGAs Break Through Performance Barriers with Industry's First Single-Chip, Dual 100G Transponder
Latest News
- Rambus Unveils HBM4E Controller: 16 GT/s, 2,048-Bit Interface, Enabling C-HBM4E
- AimFuture, a Leader in Home Appliance NPUs, to Integrate Mesacure Company’s AI Algorithms
- Security in the Quantum Era: From Cryptography to Trust — ICTK Introduces a Hardware Trust Foundation for the Quantum Era
- TES unveils a next-generation Elliptic Curve Digital Signature Algorithm (ECDSA) IP Core for Secure IoT, Blockchain, and Industrial Systems
- Seligman Ventures Leads Cognichip’s $60M Series A to Back Physics-Informed AI for Chip Design, Intel CEO Lip-Bu Tan and Seligman Ventures’ Umesh Padval Join the Board