Ultra low power C-programmable Baseband Signal Processor core
NXP has introduced a new embedded DSP core for ultra low power applications.
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Ultra low power C-programmable Baseband Signal Processor core
NXP has introduced a new embedded DSP core for ultra low power applications.
Ultra low power C-programmable DSP core
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration…
I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP desig…
The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO)…
I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, User Register Interface, No CPU Required
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal conf…
Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Version 1.8 Now Supports Spartan™-3/3E/3A The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer co…
The I2C (Inter - Integrated Circuit) protocol is a widely used serial communication protocol for transferring data between electr…
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
Modular, high performance 5G NR Layer 1 (PHY) solutions for Non-Terrestrial Network applications
AccelerComm’s physical layer solution is optimised for 5G satellite hybrid networks and related applications.
Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
To transfer the sensor data with minimal software and hardware, FLIR has developed the VoSPI protocol, an SPI based Video Interfa…
Audio Weaver - Audio Algorithm Generator tool (Design, Develop, Deploy)
Audio Weaver® an Audio SW Development Platform, an Audio drag and drop EDA suite if you like, to streamline the audio algorithm S…
The I2C Slave IP Core implements an I2C Slave fully compliant to the I2C-bus specification and user manual Rev.
The I2C Master IP Core implements an I2C Master fully compliant to the I2C-bus specification and user manual Rev.
DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated …
ColdFire V2 Core with AMBA peripherals connected in a subsytem
Building upon the 68K foundation, ColdFire offers RISC performance with industry- code density and a rich set of connectivity per…